The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to employing low temperature deposition techniques to develop a field effect transistor (FET) device.
The dimensions of semiconductor FETs have steadily shrunk as scaling to smaller dimensions leads to continuing device performance improvements. Planar FET devices typically have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate oxide. Current through the channel is controlled by applying voltage to the conducting gate. With conventional planar FET scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional geometries that will facilitate continued device performance improvements. One such class of device is a fin field effect transistor (finFET).